Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a high-speed clock alignment training operation required in a semiconductor device.
In a system constructed with a plurality of semiconductor devices, the semiconductor devices are to store data. For instance, when a data processing apparatus such as a memory control unit (MCU) requires data, the semiconductor device outputs data corresponding to addresses inputted from a device requiring the data or stores data provided from the data requiring device at a position corresponding to the addresses.
For this purpose, a conventional semiconductor device operating at a high speed may be designed to input/output two data (e.g., two bits of data) between a rising edge and a falling edge of a system clock provided from the outside and to input/output two data between the falling edge and the next rising edge. That is, the semiconductor device is designed to input/output 4 data during one period of the system clock.
However, since the system clock is expressed by two states, i.e., a logic high level and a logic low level, there is required a data clock having a frequency two times greater than that of the system clock to input/output the 4 data during one period. That is, a dedicated clock for the data input/output is required.
Therefore, the semiconductor device operating in the high speed uses the system clock as a reference clock when transmitting and receiving addresses and commands and a data clock as the reference clock when inputting/outputting data, so that the data clock is controlled to have a frequency that is twice that of the system clock.
That is, two periods of the data clock correspond to one period of the system clock and the data input/output occurs at a rising edge and a falling edge of the data clock, so that 4 data (e.g., four bits) may be inputted/outputted during one period of the system clock.
Unlike a conventional double data rate (DDR) synchronous semiconductor device using one system clock as the reference clock to perform a read or write operation, the semiconductor device operating in the high speed transmits or receives data using two clocks having different frequencies from each other to perform the read or write operation.
However, if phases of the system clock and the data clock are not aligned with each other, timings for transmission of operational commands and addresses are not aligned with timings for transmission of the corresponding data. Thus, the semiconductor device operating in the high speed may not operate normally.
Therefore, for the normal operation of the semiconductor device operating in the high speed, the interface training between the semiconductor device and the data processing device should be performed during the initial operation of the semiconductor device.
Herein, the interface training is to train the semiconductor device for operation where the interface for transferring data, commands and addresses is optimized before the normal operation between the semiconductor device and the data processing device is performed.
The interface training is classified into the address training, the clock alignment training, i.e., WCK2CK training, the read training and the write training. Among them, an operation for aligning the data clock and the system clock is performed in the clock alignment training.
FIG. 1 illustrates a block diagram of a conventional circuit for performing a clock alignment training operation.
First of all, according to a basic principle of the clock alignment training, the semiconductor device operating in the high speed receives an address signal and a command signal from an external controller based on system clocks BUF_HCK and BUF_HCKB and outputs data stored therein to the external controller based on data clocks BUF_WCK and BUF_WCKB as described above.
Therefore, if there is the phase difference between the system clocks BUF_HCK and BUF_HCKB and the data clocks BUF_WCK and BUF_WCKB, the data stored in the semiconductor device may arrive at the external controller in advance or with a delay, where the advance or delay time corresponds to the phase difference.
Thus, at the beginning of the operation of the semiconductor device operating in the high speed, the clock alignment training is performed to detect the phase difference between the system clocks BUF_HCK and BUF_HCKB and the data clocks BUF_WCK and BUF_WCKB provided from the external controller and to reduce the phase difference between the system clocks BUF_HCK and BUF_HCKB and the data clocks BUF_WCK and BUF_WCKB by transmitting the detected result to the external controller.
That is, the conventional circuit for performing the clock alignment training described in FIG. 1 is a circuit for detecting the phase difference between the system clocks BUF_HCK and BUF_HCKB and the data clocks BUF_WCK and BUF_WCKB after receiving the system clocks BUF_HCK and BUF_HCKB and the data clocks BUF_WCK and BUF_WCKB from the external controller and transmitting the detected result to the external controller.
Referring to FIG. 1, the circuit includes a clock input block 100 to receive positive and negative clocks HCK and HCKB and generate the system clocks BUF_HCK and BUF_HCKB for synchronizing input points of the address signal and the command signal and receive positive and negative clocks WCK and WCKB and generate the data clocks BUF_WCK and BUF_WCKB for synchronizing input points of data signals from the external controller, wherein the data clocks BUF_WCK and BUF_WCKB have a frequency greater than that of the system clocks BUF_HCK and BUF_HCKB, a clock frequency dividing block 120 for generating a plurality of multi-phase data frequency division clocks IWCK, QWCK, IWCKB and QWCKB each of which has the phase difference of a predetermined size after dividing the frequency of the data clocks BUF_WCK and BUF_WCKB, a phase detecting block 160 for detecting phases of the system clocks BUF_HCK and BUF_HCKB based on a phase of a selected clock IWCK or IWCKB among the plurality of multi-phase data frequency division clocks IWCK, QWCK, IWCKB and QWCKB and generating a training information signal WCK2CK_INFO in response to the detected result, and a signal transmitting block 170 for transferring the training information signal WCK2CK_INFO to the outside.
The clock frequency dividing block 120 among the components of the conventional circuit for performing the clock alignment training performs an operation of generating the plurality of multi-phase data frequency division clocks IWCK, QWCK, IWCKB and QWCKB each having the phase difference of 90 degrees (that is, quadrature phase components) using a positive data clock WCK and a negative data clock WCKB inputted thereto in a state of having the phase difference of 180 degrees, wherein the positive and negative data clocks WCK and WCKB are inputted in a differential state.
At this time, it is difficult to predetermine the generating order of phases of the plurality of multi-phase data frequency division clocks IWCK, QWCK, IWCKB and QWCKB generated in the clock frequency dividing block 120 in comparison to the data clocks BUF_WCK and BUF_WCKB.
That is, if the positive data clock WCK has a logic high level and the negative data clock WCKB has a logic low level at a moment where the clock frequency dividing block 120 starts to operate, the plurality of multi-phase data frequency division clocks IWCK, QWCK, IWCKB and QWCKB are sequentially generated to have phases of 0 degree (IWCK), 90 degrees (QWCK), 180 degrees (IWCKB) and 270 degrees (QWCKB), respectively, in comparison to a phase of the positive data clock WCK.
On the other hand, if the positive data clock WCK has a logic low level and the negative data clock WCKB has a logic high level at the moment where the clock frequency dividing block 120 starts to operate, the plurality of multi-phase data frequency division clocks IWCK, QWCK, IWCKB and QWCKB are sequentially generated to have phases of 180 degrees (IWCK), 270 degrees (QWCK), 0 degree (IWCKB) and 90 degrees (QWCKB), respectively, in comparison to the phase of the positive data clock WCK.
Although there is a state where the operation of the clock frequency dividing block 120 cannot be predetermined through the design, an operation of comparing the phases of the system clocks BUF_HCK and BUF_HCKB and that of the selected clock IWCK or IWCKB among the plurality of multi-phase data frequency division clocks IWCK, QWCK, IWCKB and QWCKB generated in the clock frequency dividing block 120 is always performed in the preset order.
Therefore, in the case where the plurality of multi-phase data frequency division clocks IWCK, QWCK, IWCKB and QWCKB is sequentially generated to have the phases of 0 degree (IWCK), 90 degrees (QWCK), 180 degrees (IWCB) and 270 degrees (QWCKB) in comparison to the phase of the positive data clock WCK, by moving the phases of the data clocks BUF_WCK and BUF_WCKB by the maximum half period, i.e., 0.5*tck, it is possible to synchronize the phases of the system clocks BUF_HCK and BUF_HCKB with those of the data clocks BUF_WCK and BUF_WCKB, so that the clock alignment training operation can be completed within a comparatively short time.
In the meantime, in the case where the plurality of multi-phase data frequency division clocks IWCK, QWCK, IWCKB and QWCKB is sequentially generated to have the phases of 180 degrees (IWCK), 270 degrees (QWCK), 0 degree (IWCKB) and 90 degrees (QWCKB) in comparison to the phase of the positive data clock WCK, since the operation of synchronizing the phases of the system clocks BUF_HCK and BUF_HCKB with those of the data clocks BUF_WCK and BUF_WCKB should be performed by moving the phases of the data clocks BUF_WCK and BUF_WCKB by the maximum one period, i.e., 1*tck, it may take a relatively larger time until the clock alignment training operation is completed.